Specification
• Chipset:lntel350-T2
• Host lnterface: PCl Express·2.1 5GT/slanex1 lane
• Supports10/100/1000Mbps data rate auto negotiation
• Each port can send and receive eight queue
• Up to 86 pieces of queue receiver to adjust(RSS) in multiple processor system can minimize the use of the CPU
• Support 8 pool of each ports(a single queue) virtual machine device queue(VMDq)
• Support the SR- IOVfunction
• Support direct cache access(DCA)
• Support the lntel l/0V3.0 acceleration technology
• TS0 interleaved technique isto reduce the delay
• To minimize the equipment l/0 interrupt using MSl and MSl -X
• The UDP and TCP and lP checksum partial load
• The UDP and TCP send piecewise load(TS0)
• SCTP receiving and sending oheckand partial load
• The packet combination of interrupt and timer(packet timer) and absolute- interruption
• delay timer is to send and receive operation
• Support PCl Express base specification 2.0(5GTs)
• lntel l350AM4double integrated MAC+ PHY and SERDES chip oontroller with high
• performance, high reliability and low power consumption characteristics
• Super depth, based on the packet buffer perchannel can reduce the use ofthe CPU
• Hardware acceleration can be partial load taskfrom the main processor The controller can be used for partial load TCP/UDP/lP checksum TCP segment
• Server level of reliability, availability and performance characteristics:
• Link aggregation and load balancing
• Relevant switches: 802.3AD(LACP), common Trunking(GEC/FEC)
• Exchange and NIC norelated
Application
• Desktop computers, workstations and servers
System Reguirement
• Windows XP/7/8/10/ista/Server2003/Server2008/Server2012/ Linux2.4.xor above
Package Content
• 1xPCIe x1 to 2 Ports 1G Server Lan Card
• 1xLow profile bracket
Note: Contents may vary depending on country/market
